Experince: 6 Years
Note: We are seeking a Design Verification Engineer with strong SV, UVM and AXI experince.
Technical:
Strong expertise along-with complex SoC/IP debug is must
At-least 5 years of experience in System Verilog HVL and C/C .
AMBA AXI bus along-with ARM or C based processor
Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
Low Power Verification in UPF/net-list Simulation good to have
Make/Perl/Python
Ensure customer satisfaction.
Reporting to customer on daily or weekly progress effectively
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.