We are seeking a Design Verification Engineer with experience in developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs, including compute arrays, DMAs, NoCs, and memory subsystems.
Location: San Jose, CA (Complete Onsite)
Experience Range: 8 to 15 years
Key Skills: SV/UVM, PCIe/Ethernet/HBM
What You'll Be Doing:
- Developing strong SV/UVM scale test benches
- Gaining expertise in AXI, NOC/Crossbar, and performance optimization
- Managing regression/triage and coverage closure
- Working on Amazon tools, flows, and methodologies in a start-up mode environment with minimal documentation
What We Are Looking For:
- A bachelor’s degree in Electrical or Computer Engineering with a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline
- Experience in verification closure with a team
- Proficiency in Make/Perl/Python
- Ability to ensure customer satisfaction
- Effective reporting to customers on daily or weekly progress
Nesco Resource offers a comprehensive benefits package for our associates, which includes a MEC (Minimum Essential Coverage) plan that encompasses Medical, Vision, Dental, 401K, and EAP (Employee Assistance Program) services.
Nesco Resource provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws.
